In recent years, a semiconductor device has been known in the field of semiconductor devices used in power applications. This vertical semiconductor device makes it possible to achieve both the enhancement of breakdown voltage and the reduction of on-state resistance and has a PN column layer that functions as a super junction (SJ) as a drift layer. This semiconductor device will be hereafter abbreviated as SJ-MOS transistor. The SJ-MOS transistor is disclosed in, for example, JP-A-2004-72068 (i.e., Patent Document 1).
FIGS. 22A and 22B are sectional views schematically illustrating a conventional typical SJ-MOS transistor 90. FIG. 22A illustrates the repetitive unit structure of the SJ-MOS transistor 90 and FIG. 22B illustrates the SJ-MOS transistor 90 comprised of the unit structures in FIG. 22A. When the unit structure illustrated in FIG. 22A is sequentially inverted at the axes of symmetry A1-A1, A2-A2 indicated by alternate long and short dash lines and repeated, the SJ-MOS transistor 90 illustrated in FIG. 22B is constructed.
The SJ-MOS transistor 90 illustrated in FIGS. 22A and 22B is an N-channel SJ-MOS transistor and uses a silicon substrate composed of an N-type (n+) semiconductor layer 1 as a drain region. Over the N-type semiconductor layer 1, a PN column layer 10 having a thickness of d is formed. The PN column layer is formed by alternately and repetitively disposing an N-type column 20n and a P-type column 20P, identical in impurity concentration (i.e., X0n=X0p) and width (i.e., W0n=W0p) with each other, that are epitaxial layers composed of silicon. The columns are abutted against one another. Over the PN column layer 10, a P-type (p−) semiconductor layer (i.e., a base region) 3 that is an epitaxial layer composed of silicon and functions as a channel formation layer is formed. In other words, the SJ-MOS transistor 90 is a semiconductor device constructed as illustrated in FIG. 22B. That is, the N-type semiconductor layer 1 is formed in abutment with a first interface B1 of the PN column layer 10 and the P-type semiconductor layer 3 is formed in abutment with a second interface B2 of the PN column layer 10.
In the surface part of the P-type semiconductor layer 3, an N-type (n+) region 4 as a source region is selectively formed. A P-type (p+) region 3a connected to a source electrode in common next to the N-type region 4 is a contact region formed to fix the potential of the P-type semiconductor layer 3. An insulating gate electrode 7 of trench structure comprised of a side wall insulating film 5 and buried polycrystalline silicon 6 is formed next to the N-type region 4 so that it penetrates the P-type semiconductor layer 3. Though not shown in the drawings, the N-type columns 20n, P-type columns 20p, N-type regions 4, P-type regions 3a and insulating gate electrodes 7 in the SJ-MOS transistor 90 are arranged in a stripe pattern perpendicular to the surfaces of FIGS. 22A and 22B in the substrate surface.
The SJ-MOS transistor 90 illustrated in FIGS. 22A and 22B is characterized in that it has the PN column layer 10 that functions as a super junction. This makes it a semiconductor element excellent in achieving both the enhancement of breakdown voltage and the reduction of on resistance as compared with conventional vertical MOS transistors (DMOS transistors) without a PN column layer. More specific description will be given. In the SJ-MOS transistor 90, the N-type columns 20n of the PN column layer 10 function as a drift layer when the transistor is turned on. The P-type columns 20p have a function of expanding a depletion layer to the N-type columns 20n that are a current path when the transistor is off. In a DMOS transistor without a P-type column, a problem arises when the concentration of the N-type layer as a drift layer is increased. The depletion layer is not expanded and the breakdown voltage is lowered. In the SJ-MOS transistor 90 in FIGS. 22A and 22B, meanwhile, the following can be implemented even when the N-type columns 20n as a drift layer is increased in impurity concentration and lowered in on resistance: when the transistor is off, the depletion layer can be expanded to the N-type columns 20n by appropriately setting the impurity concentration of the P-type columns 20p and the like; and thus both the enhancement of breakdown voltage and the reduction of on resistance can be achieved.
[Patent Document 1] JP-A-2004-72068
To obtain a high breakdown voltage in the SJ-MOS transistor 90 in FIGS. 22A and 22B, as mentioned above, it is required to expand the depletion layer to the N-type columns 20n as a drift layer. To expand the depletion layer to the N-type columns 20n, the following condition is imposed: “the impurity amount (=concentration×volume) of the N-type columns 20n and the impurity amount (=concentration×volume) of the P-type columns 20P shall be made equal to each other.” The PN column layer 10 is designed so as to meet this condition. However, there is a problem. If variation in shape processing or variation in impurity concentration (hereafter, collectively referred to as variation in formation) is produced when the PN column layer 10 is formed, the above condition cannot be met. For this reason, the expansion of the depletion layer in the drift layer is prevented by a surplus of the impurity amount of the N-type columns 20n or the P-type columns 20p and the breakdown voltage of the SJ-MOS transistor 90 is lowered. The reduction in breakdown voltage due to the above variation in formation becomes more apparent as the on resistance of the SJ-MOS transistor 90 is reduced. That is, since the impurity amount of the N-type columns 20n is increased to reduce on resistance, it is required to similarly increase the impurity amount of the P-type columns 20p as well. As a result, variation in a surplus of impurities caused by variation in formation is relatively increased. For this reason, variation in breakdown voltage is more increased by the above variation in formation as the impurity amount of the N-type columns 20n is increased to reduce the on resistance of the SJ-MOS transistor 90.
To cope with the above problem specific to the SJ-MOS transistor, Patent Document 1 proposes a taper structure. In the semiconductor element disclosed in Patent Document 1, a taper angle is provided in the joint areas between the N-type columns and the P-type columns in a PN column layer. In this taper structure, the width of the N-type columns and the width of the P-type columns are varied in opposite directions from the principal surface side toward the back side in the PN column layer. In this structure, as a result, the impurity amount of the N-type columns and the impurity amount of the P-type columns are also varied in opposite directions. Therefore, even when the above variation in formation is produced, a region where the above condition of equal impurity amounts is met exists somewhere in the depth of the PN column layer. Thus the depletion layer can be expanded to the N-type columns in this region. Even in the above taper structure, however, a region where the above condition of equal impurity amounts is met is limited to some narrow region in the PN column layer and variation in breakdown voltage due to variation in formation is still large.